1. Field
Subject matter disclosed herein relates to non-volatile flash memory.
2. Information
Flash memories typically preserve stored information even in power-off conditions. In such memories, in order to change a logic state of a cell, e.g. a bit, an electric charge present in a floating gate of the cell may be changed by application of electric potentials to various portions of the cell. A “0” state typically corresponds to a negatively charged floating gate and a “1” state typically corresponds to a positively charged floating gate. As intended, a non-volatile memory may preserve stored information over time, but a reliability of such a memory may be limited by degenerative processes affecting a tunnel oxide of the memory during various programming and erasing cycles. As a cell is programmed and erased, electrons move to and from the floating gate through the tunnel oxide. Such electrons may create “traps” in the oxide (i.e., defects in the oxide in which electrons may be trapped). Traps created in the tunnel oxide are typically responsible for stress induced leakage current (SILC), which is a leakage current typically observed at relatively low electric fields. Trap density may increase with the number of program and erase cycles experienced by the tunnel oxide. Due to the presence of these traps, a programmed or erased floating gate may, show an enhanced charge loss and/or charge gain even under relatively low electric fields across the tunnel oxide commonly seen during normal conditions of storage and reading of the cell. Such low level charge loss and/or charge gain mechanisms, which may lead to information loss, are undesirable since flash memory devices are expected to be able to store information on the order of at least several years.
A physical model underlying SILC includes a trap assisted tunnel (TAT) model. A current loss, depending on its direction, may either lead to a charge gain or a charge loss. A charge gain may correspond to information loss for a “1” state, whereas a charge loss may correspond to information loss for a “0” state. In either case, such a logic state determined by charge on a floating gate may be lost, possibly leading to a memory failure. For example, a failure of the “0” state may occur if enough electrons flow from the floating gate to a substrate to reduce a threshold voltage of the memory cell affected by SILC to below a value used to discriminate a “0” state from a “1” state. Such a failure may be called a retention failure. In another example, a failure of the “1” state may occur on an erased cell belonging to the same word-line of a read cell. Such a cell may suffer a parasitic gate stress, which can induce a tunnel current from the substrate to the floating gate, possibly leading to unwanted programming. Such a condition is called read disturb and may be particularly pronounced on cells affected by SILC.
SILC is typically dependent on tunnel oxide thickness. SILC may strongly increase for tunnel oxide thicknesses below approximately 10 nm, for example. In addition, SILC strongly depends on the strength of an electric field applied to the tunnel oxide. Accordingly, SILC is a relatively important factor limiting the scaling of tunnel oxide thickness in flash memories.